(1) Field of the Invention
The present invention relates to semiconductor devices such as BiCMOSs and CMOSs having integral P- and N-type elements, and more particularly to a structure of an element isolation region which isolates the elements from one another as well as a method for fabricating the same.
(2) Description of the Related Art
With a recent trend of making semiconductor devices further miniaturized in the structure and higher in the integration density, there is a need of miniaturizing the structure of the element isolation region that electrically isolates elements from one another. Such an element isolation region is constituted by, for instance, a selective oxide film (or field oxide film) which is fabricated by an LOCOS process and, to reinforce the element isolation performance of the field oxide film, a channel stopper is formed thereunder by introducing an impurity. FIGS. 1A to 1D illustrate step by step a prior art process of fabricating such an element isolation region, a P- and an N-channel region being shown separately.
As shown in FIG. 1A, on a semiconductor substrate 11 which has a predetermined semiconductor surface region formed on the principal surface side, a first silicon oxide film 22 is formed, and a silicon nitride film 23 is formed thereon. As shown in FIG. 1B, with a first resist pattern 24 formed by a lithographic process as a mask, a portion of the silicon nitride film 23 which is in an element isolation formation region is removed until the first silicon oxide film 22 or the semiconductor substrate 11 is exposed.
Next, as shown in FIG. 1C, the first resist pattern 24 is removed. Then, a second resist pattern 25 is formed to cover the P-channel region, and a P-type impurity layer 20' is formed as a channel stopper in the N-channel region by ion implanting a P-type impurity such as boron. As shown in FIG. 1D, the second resist pattern 25 is subsequently removed, and a second silicon oxide film (or field oxide film) 14 is formed by oxidation for element isolation. Finally, the silicon nitride film 23 is removed.
In this element isolation structure, no impurity for the channel stopper is doped immediately under the field oxide film 14 for the P-channel region element isolation. Therefore, to obtain the desired element isolation effect, it is necessary to increase the width or thickness dimension of the field oxide film. Thus, it is difficult to make the element isolation region finer as compared to the channel region.
It has been proposed to improve the element isolation with respect to the P-channel region by implanting an impurity for the N-channel stopper immediately under the field oxide film in the P-channel region as well. FIGS. 2A to 2E illustrate step by step a fabrication process in this case. As shown in FIG. 2A, on a semiconductor substrate 11, a first silicon oxide film 22 is formed, and a silicon nitride film 23 is formed thereon. As shown in FIG. 2B, with a first resist pattern 24 formed as a mask by a lithographic process, a portion of the silicon nitride film 23 in the element isolation formation region is removed until the first silicon oxide film 22 or the semiconductor substrate 11 is exposed.
Next, as shown in FIG. 2C, the first resist pattern 24 is removed. Then, a second resist pattern 25 is formed to cover the P-channel region, and a P-type impurity layer 20' is formed as a channel stopper in the N-channel region by ion implanting a P-type impurity such as boron in a portion at which the second resist pattern 25 does not exist. As shown in FIG. 2D, the second resist pattern 25 is subsequently removed. Then, a third resist pattern 26 covering the N-channel region is formed, and an N-type impurity layer 19' is formed as a channel stopper of the P-channel region by ion implanting an N-type impurity such as boron in a portion at which the third resist pattern 26 does not exist. As shown in FIG. 2E, the third resist pattern 26 is subsequently removed, and a second silicon oxide film (or field oxide film) 14 is formed by oxidation for element isolation. Finally, the silicon nitride film 23 is removed.
As shown above, it is possible to realize a finer isolation element with respect to the individual channel regions by forming the channel stoppers immediately under the field oxide film in the respective P- and N-channel regions. However, to fabricate this structure, it is necessary to form resist patterns each for the ion implantation of impurity in each channel region, thus increasing the number of steps and the fabrication cost.
Another problem is posed by the fact that, since the channel stoppers, which are formed immediately under the field oxide film in the respective channel regions, are of relatively high impurity concentration, active layers formed by an impurity of the opposite conductivity type in each channel region, for instance, source and drain regions of a MOS transistor, may happen to be in direct contact with the channel stoppers. As an example, in the case of the example shown in FIG. 3, a P-type impurity layer 20' is formed as the channel stopper immediately under a field oxide film 14 in a P-channel region such that it is in contact with an N-type diffusion layer 18 which constitutes the source and drain of an N-type MOS transistor. A P-N junction that is formed between these two high impurity concentration impurity layers, is subject to P-N junction breakdown voltage deterioration. Besides, the impurity in the N-type diffusion layer 18 is diffused laterally by a heat treatment during the fabrication process. As a consequence, a pronounced MOS transistor narrow channel effect appears and results in deterioration of the transistor characteristics.